SCHEMATIC REV 4.2 // SYNTHESIS IN PROGRESS
IT - ITALIANO
Sito in Costruzione
DANIELE SALADINO // 6x IN-14 NIXIE GAS-DISCHARGE ARRAY
RTC LOCAL 24H
8
2
8
2
8
5
8
4
8
1
8
9
Stiamo progettando l'architettura hardware, i circuiti stampati ad alta velocità e l'infrastruttura firmware bare-metal. Il sistema sarà presto operativo.
SILICON TARGET
FPGA + STM32H7
Dual-Core 480 MHz ARM M7/M4
BUS PROTOCOL
PCIe & CAN-FD
Differential Impedance: 90Ω
RTOS KERNEL
Zephyr / FreeRTOS
Deterministic Microsecond Latency
DS-CORE
ELECTRONICS DESIGNER
BGA-256 BALL GRID ARRAY // DIE INTERCONNECT ACTIVE
LOGIC ANALYZER / OSCILLOSCOPE
● CH1: 3.30V (SQUARE)
● CH2: 1.82V (CLOCK)
TRIG: RISING [AUTO]
[00:24:12]
HDL_COMPILER:
Synthesizing Verilog top_module.v ... OK
[00:24:13]
DRC_CHECK:
Trace clearance 0.15mm passed. Differential pair skew: 0.02ps
[00:24:14]
NETLIST:
Routing high-speed memory bus layer 3 (GND/SIG/SIG/PWR)